1. Field of the Invention
The present invention relates to an internal voltage generation circuit for a semiconductor device circuit for converting an external voltage to an internal voltage, and more particularly to an improved internal voltage generation circuit for a semiconductor device which directly supplies the external voltage to the semiconductor device when a level of the external voltage is low.
2. Description of the Background Art
FIG. 1 is a circuit view of a conventional internal voltage generation circuit for a semiconductor device. As shown therein, the conventional internal voltage generation circuit includes a voltage generating unit 1 for converting the level of external voltage Vcc in accordance with reference voltage Vref applied thereto, a driving unit 2 for receiving an output signal of the voltage generating unit 1 and internal voltage Vdd and outputting a predetermined level of the internal voltage Vdd, and an NMOS transistor N11 connected between the driving unit 2 and the ground and for being enabled in accordance with an enable signal Ea.
The voltage generating unit 1 includes an PMOS transistor P11 receiving the reference voltage Vref through its gate, its source connected to the external voltage Vcc, and its drain connected to node Na, and PMOS transistors P12, P13, P14 serially connected between the node Na and the ground, wherein the gate and drain of each of the PMOS transistors P12, P13, P14 are connected to each other.
The driving unit 2 includes a differential amplifier DF with its input terminals connected to the node Na and node Nc serving as an output terminal and a PMOS transistor P15 receiving an output signal of the differential amplifier DF through its gate, its source connected to the external voltage Vcc, and its drain connected to the output terminal Nc.
As shown in FIG. 2, the differential amplifier DF includes: a PMOS transistor P21 with its source connected to the external voltage Vcc and its drain and gate connected to each other; a PMOS transistor P22 which forms an current mirror together with the PMOS transistor P21; an NMOS transistor N21 with its drain connected to that of the PMOS transistor P21 and its gate connected to the node Na of the voltage generating unit 1; an NMOS transistor N22 with its gate connected to the output terminal Nc of the driving unit 2, and its size being identical to that of the NMOS transistor N21; and an NMOS transistor N23 with its drain connected to each source of the NMOS transistors N21, N22.
The operation of the conventional internal voltage generation circuit will now be described.
A reference voltage Vref applied to the gate of the PMOS transistor P11 in the voltage generating unit 1 and a current I flowing through the PMOS transistor P11 is as following equation 1: EQU I=k(V.sub.GS -V.sub.T).sup.2 ( 1)
wherein, V.sub.GS is a gate-source voltage of the PMOS transistor P11, V.sub.T is a threshold voltage, and k is a proportional constant.
If the PMOS transistors P12, P13, P14 in the voltage generating unit 1 which are connected with the PMOS transistor P11 in series respectively have the same size as the PMOS transistor P11, the gate-source voltage V.sub.GS of the respective PMOS transistors is obtained by an equation 2 as follows: EQU V.sub.GS =V.sub.T +.alpha. (2)
wherein, .alpha. is ##EQU1##
According to equation 1, a voltage Va at the node Na, the drain of the PMOS transistor P11, is obtained as 3V.sub.GS by calculation of the voltage V.sub.GS times three. Also, in the case in which the external voltage Vcc and the reference voltage Vref are identically increased or decreased, the voltage Va constantly remains at 3V.sub.GS.
The voltage Va is applied to the gate of the NMOS transistor N21 of the differential amplifier DF in FIG. 2, and the internal voltage Vdd is applied to the gate of the NMOS transistor N22 disposed opposite the NMOS transistor N21. The voltage Va and the internal voltage Vdd are compared to each other, whereby the compared value is transmitted to the gate of the PMOS transistor P15 with its source connected to the external voltage Vcc and its drain connected to the output terminal Nc.
Meanwhile, the NMOS transistor N23 commonly connected to the sources of the two NMOS transistors N21, N22 becomes current source in accordance with an enable signal Eb applied to the gate thereof.
Here, the differential amplifier DF, the PMOS transistor P15 and the output terminal Nc form a closed loop, so that the internal voltage Vdd becomes identical to the voltage Va, and the internal voltage Vdd value is obtained by an equation 3 as follows: EQU Vdd=V.sub.GS =3(V.sub.T +.alpha.) (3).
The value of internal voltage Vdd obtained from equation 3 becomes an ultimate internal voltage Vdd in order to be supplied into a semiconductor device (not shown) as an internal voltage.
However, when the level of the external voltage Vcc is lowered, an operation region of the PMOS transistor P11 which receives the reference voltage Vref via the gate thereof is transitted from a saturation region to a linear region.
The PMOS transistor P11 operates in the linear region, so that the voltage Va at the node Na becomes significantly reduced, thereby lowering the level of the internal voltage Vdd.
When the internal voltage being outputted is reduced, the operating speed of the semiconductor device (not shown) being operated by the internal voltage Vdd is disadvantageously decreased as well.
As described above, in the conventional internal voltage circuit for a semiconductor device, a slight lowering of the level of the external voltage Vcc causes the internal voltage Vdd being supplied to the semiconductor device to be abruptly reduced and accordingly the internal voltage Vdd is changed in a large magnitude, whereby the operation of the semiconductor device being operated by the internal voltage is seriously influenced.